{"product_id":"rtl-modeling-with-systemverilog-for-simulation-and-synthesis-using-systemverilog-for-asic-and-fpga-design","title":"RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design","description":null,"brand":"Createspace Independent Publishing Platform","offers":[{"title":"Default Title","offer_id":39328183517284,"sku":"9781546776345","price":149.95,"currency_code":"EUR","in_stock":true}],"url":"https:\/\/suomalainen-test.myshopify.com\/products\/rtl-modeling-with-systemverilog-for-simulation-and-synthesis-using-systemverilog-for-asic-and-fpga-design","provider":"Suomalainen Test","version":"1.0","type":"link"}